Field
The present disclosure relates generally to layout construction, and more particularly, to a multiple split rail ultra-high performance standard cell library architecture.
Background
A standard cell is an integrated circuit that may be implemented with digital logic. An application-specific integrated circuit (ASIC), such as a system-on-a-chip (SoC) device, may contain thousands to millions of standard cells. Reducing a size/area footprint of ASICs is beneficial. Reducing a size of the process technology may allow for the size/area footprint of ASICs to be reduced. Standard power rail designs may be unavailable or insufficient for certain smaller process technologies (e.g., 10 nm). Accordingly, there is a need for new power rail designs, such as for example, when standard power rail designs are unavailable or insufficient.